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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:20:30 06/03/2019 
-- Design Name: 
-- Module Name:    V_ALARM - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity V_ALARM is
    Port ( M : in  STD_LOGIC;
           K : in  STD_LOGIC;
           D : in  STD_LOGIC;
           V : in  STD_LOGIC;
           S : inout  STD_LOGIC);
end V_ALARM;

architecture Behavioral of V_ALARM is

begin
     S <= (M AND (NOT K)) AND ((S OR V) OR D);

end Behavioral;