PROJECT Project Status
Project File: PROJECT.xise Parser Errors: X 1 Error
Module Name: PROJECT Implementation State: Synthesized
Target Device: xc7a100t-3csg324
  • Errors:
X 5 Errors (0 new)
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Current Errors [-]
Synthesis Errors 
ERROR:HDLCompiler:1206: - "C:\Users\Maambo\Desktop\Academic data\EEE3131\PROJECT\PROJECT.vhd" Line 42: Syntax error near '{' 
ERROR:HDLCompiler:1206: - "C:\Users\Maambo\Desktop\Academic data\EEE3131\PROJECT\PROJECT.vhd" Line 42: Syntax error near '}' 
ERROR:HDLCompiler:806: - "C:\Users\Maambo\Desktop\Academic data\EEE3131\PROJECT\PROJECT.vhd" Line 42: Syntax error near "{". 
ERROR:HDLCompiler:69: - "C:\Users\Maambo\Desktop\Academic data\EEE3131\PROJECT\PROJECT.vhd" Line 42: <s> is not declared. 
ERROR:HDLCompiler:854: - "C:\Users\Maambo\Desktop\Academic data\EEE3131\PROJECT\PROJECT.vhd" Line 39: Unit <behavioral> ignored due to previous errors. 
 
Current Warnings [-]
No Warnings Found
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri 17. May 07:45:50 2019X 5 Errors (0 new)00
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 05/24/2019 - 03:19:51