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-- Company: 
-- Engineer: 
-- 
-- Create Date:    07:12:06 05/17/2019 
-- Design Name: 
-- Module Name:    PROJECT - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity PROJECT is
    Port ( D : inout  STD_LOGIC;
           V : inout  STD_LOGIC;
           K : inout  STD_LOGIC;
           M : inout  STD_LOGIC);
end PROJECT;

architecture Behavioral of PROJECT is

begin
     S <= {[ D AND (NOT V) AND (NOT K)] OR V AND (NOT K)} AND M AND (NOT K);	  
		

end Behavioral;