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-- Company: 
-- Engineer: 
-- 
-- Create Date:    06:21:17 05/24/2019 
-- Design Name: 
-- Module Name:    FLIP_FLOP - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FLIP_FLOP is
    Port ( S : inout  STD_LOGIC;
           P : in  STD_LOGIC);
end FLIP_FLOP;

architecture Behavioral of FLIP_FLOP is

begin
     S <= (P NOR (NOT S)) OR ((NOT P) NOR S);

end Behavioral;