Carsec Project Status
Project File: Carsec.xise Parser Errors: No Errors
Module Name: Carsec Implementation State: Synthesized
Target Device: xc7a100t-3csg324
  • Errors:
 No Errors
Product Version:ISE 14.7
  • Warnings:
 No Warnings
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice LUTs 1 63400 0%
Number of fully used LUT-FF pairs 0 1 0%
Number of bonded IOBs 3 210 1%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue 14. May 18:53:54 2019000
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 05/16/2019 - 17:48:31